ASTERS: Adaptable Threshold Spike-timing Neuromorphic Design with Twin-Column ReRAM Synapses
TimeThursday, July 14th3:30pm - 3:50pm PDT
Location3005, Level 3
Emerging Models of Computation
DescriptionComplex event-driven and neuron dynamics was an obstacle to implementing efficient brain-inspired computing architectures with VLSI circuits. To solve this problem and harness the event-driven advantage, we propose ASTERS, a resistive random-access memory (ReRAM) based neuromorphic design to conduct the time-to-first-spike SNN inference. In addition to the fundamental novel axon and neuron circuits, we also propose two techniques through hardware-software co-design: "Multi-Level Firing Threshold Adjustment" to mitigate the impact of ReRAM device process variations, and “Timing Threshold Adjustment” to further speed up the computation. Experiments show that ASTERS achieves >34.7% energy savings while maintaining 90.1% accuracy under 20% process variations.