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Presentation

HWST128: Complete Memory Safety Accelerator on RISC-V with Metadata Compression
TimeWednesday, July 13th3:50pm - 4:10pm PDT
Location3005, Level 3
Event Type
Research Manuscript
Keywords
Hardware Security: Primitives, Architecture, Design & Test
Topics
RISC-V
Security
DescriptionMemory safety is one key security issue in modern software. Existing pointer-based memory safety methods rely on additional information to check eligibility when a pointer is dereferenced. These methods introduce significant performance overhead. Therefore, this paper aims to reduce the performance overhead by hardware/software co-design. This paper achieves complete memory safety with low performance overhead and high compatibility by utilizing microarchitecture support, pointer analysis from the compiler, and metadata compression. The system is implemented on the Xilinx FPGA and shows 3.74 times faster than existing software-based methods, evaluated by running SPEC2006 benchmark programs.