Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
TimeTuesday, July 12th1:30pm - 1:52pm PDT
Location3005, Level 3
Event Type
Research Manuscript
AI/ML Design: System and Platform
DescriptionSemantic segmentation is one of the popular tasks in computer vision, providing pixel-wise annotations for scene understanding. However, segmentation-based convolutional neural networks require tremendous computational power. In this work, a fully-pipelined hardware accelerator with support for dilated convolution is introduced. Furthermore, we propose a genetic search based automated channel pruning technique, jointly optimizing computational complexity and model accuracy. Finally, hardware heuristics and an accurate model of the FPGA accelerator design enable an hardware-aware pruning search. We achieve 2.44× lower latency with minimal degradation in semantic prediction quality (−1.98pp lower mIOU) compared to the baseline DeepLabV3+ model, evaluated on Arria-10 FPGA.