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Presentation

Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration
TimeTuesday, July 12th1:30pm - 1:53pm PDT
Location3007, Level 3
Event Type
Research Manuscript
Keywords
System-on-Chip Design Methodology
Topics
EDA
DescriptionMulti-chip integration is widely recognized as the extension of Moore's Law. Cost-saving is frequently mentioned advantage, but previous works rarely present quantitative demonstrations on the superiority over monolithic SoC. In this paper, we build a comprehensive cost model and put forward an analytical method for multi-chip systems based on three typical multi-chip integration technologies to quantitatively analyze the cost benefits from yield improvement, chiplet and package reuse, and heterogeneity. We re-examine the actual cost of multi-chip systems from various perspectives and show how to reduce the total cost of the VLSI system through appropriate multi-chiplet architecture.