Automated Accelerator Optimization Aided by Graph Neural Networks
TimeTuesday, July 12th10:53am - 11:15am PDT
Location3004, Level 3
Event Type
Research Manuscript
RTL/Logic Level and High-level Synthesis
DescriptionUsing High-level synthesis (HLS), the hardware designers must describe only a high-level behavioral flow of the design. However, it still can take weeks to develop a high-performance architecture mainly because there are many design choices at a higher level to explore. It also takes several minutes to hours to evaluate the design with the HLS tool. To solve this problem, we model the HLS tool with a graph neural network that is trained to be used for a wide range of applications. The experimental results demonstrate that our model can estimate the quality of design in milliseconds with high accuracy.