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Presentation

Algorithm/Architecture Co-Design for Energy-Efficient Acceleration of Multi-Task DNN
TimeTuesday, July 12th3:30pm - 3:54pm PDT
Location3002, Level 3
Event Type
Research Manuscript
Keywords
AI/ML Design: Circuits and Architecture
Topics
Design
DescriptionReal-world AI applications, such as augmented reality, require processing multiple CV tasks simultaneously. However, the enormous parameter size and the memory footprint have been crucial stumbling blocks for deep neural networks to be applied in resource-constrained devices. Therefore, we choose algorithm/architecture co-design approach to solve the problem. Our transfer learning algorithm, named SqueeD, reduces per-task weight and activation size to xxx% and xxx%, respectively, by sharing those data between tasks. Moreover, we design novel hardware design and dataflow to minimize off-chip memory access by fully utilizing benefits from SqueeD. In result,and our system reduce per-task energy consumption by xxx%