BlueScale: A Scalable Memory Architecture for Predictable Real-Time Computing on Highly Integrated SoCs
TimeThursday, July 14th4:30pm - 4:50pm PDT
Location3004, Level 3
Time-Critical System Design
DescriptionIn real-time embedded computing, time-predictability and performance are required simultaneously by memory transactions. However, with increasingly more elements being integrated into hardware, memory interconnects become a critical stumbling block to satisfying timing correctness, due to lack of hardware and scheduling scalability. In this paper, we propose a new hierarchically distributed memory interconnect, BlueScale, managing memory transactions using identical Scale Elements, which ensures hardware scalability. The Scale Element introduces two nested priority queues, achieving iterative compositional scheduling for memory transactions, guaranteeing scheduling schedulability. Associated with that, we present a theoretical model and optimization to further improve BlueScale’s real-time performance.