SEM-Latch: A Lost-Cost and High-Performance Latch Design for Mitigating Soft Errors in Nanoscale CMOS Process
TimeWednesday, July 13th5:06pm - 5:30pm PDT
Location3007, Level 3
Manufacturing Test and Reliability
DescriptionAs automotive electronics requirements increase, soft errors (particularly, single-event transients (SET) and single-event upsets (SEU)) become more critical.
Various SEU/SET-tolerant latches have been developed but may suffer from performance issues.
Therefore, a new latch design is proposed, SEAL, which improves area, power, timing simultaneously.
Experimental results show that SEAL decreases power, timing, and PDAP (Product of delay, area, and power) by an average of 4.5%, 38.4%, and 44.5%, respectively, compared to SEU-tolerant latches HPST and QUATRO.
Moreover, the enhanced SEAL provides 99.99983% of SET protection as AMSER-latch, but reduces the area, power, and timing overhead by 13.3%, 51.4%, and 56.1%.