ALICE: An Automatic Design Flow for eFPGA Redaction
TimeWednesday, July 13th4:10pm - 4:30pm PDT
Location3006, Level 3
Hardware Security: Attack and Defense
Hardware Security: Primitives, Architecture, Design & Test
DescriptionFabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the process to a third-party foundry requires to protect the intellectual property of the hardware designs. Designers can rely on embedded reconfigurable devices to hide the functionality of selected design portions unless the configuration string (bitstream) is provided. We propose ALICE, a design flow that addresses the EDA challenges of the FPGA redaction problem. ALICE supports the designer in the partitioning of RTL modules between reconfigurable fabrics and the rest of the circuit, automating the generation of the corresponding reconfigurable fabrics and redacted design.