PHANES: ReRAM-based Photonic Accelerators for Deep Neural Networks
TimeTuesday, July 12th10:52am - 11:15am PDT
Location3002, Level 3
In-memory and Near-memory Computing
DescriptionResistive-random-access-memory has demonstrated promises of in-situ matrix-vector-multiplications to accelerate deep neural networks. However, subject to intrinsic properties of analog processing, most proposed ReRAM-based accelerators require excessive costly ADC/DAC to avoid distortion of electronic-analog signals during inter-tile transmission. This paper presents a novel photonic-accelerator architecture (PHANES), which utilizes optical interconnects to achieve high-fidelity analog-analog links. Such paradigm calculates partial-sum during the optical transmission to reduce ADC/DAC and shift-adders. To circumvent memory-wall problem, we further propose a progressive bit-depth technique. Evaluations show that PHANES improves system energy-efficiency-per-area (TOPS/W/mm2) by 26.2x compared to state-of-the-art designs, with great potentials of scalability towards very-large-scale accelerators.