Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity and Clock Feasibility
TimeWednesday, July 13th2:37pm - 3pm PDT
Location3007, Level 3
Event Type
Research Manuscript
Physical Design and Verification, Lithography and DFM
DescriptionModern field-programmable gate arrays (FPGA) contain heterogeneous resources, including CLB, DSP, BRAM, IO, etc. A configurable logic block (CLB) slice is further categorized to SLICEL and SLICEM, which can be configured as specific combinations of instances in {LUT, FF, distributed RAM, SHIFT, CARRY}. Such kind of heterogeneity challenges existing placement algorithms. Meanwhile, limited clock routing resources also lead to complicated clock constraints. In this work, we propose a multi-electrostatic FPGA placement framework considering Multi-configuration mode CLB heterogeneity and clock feasibility. We support a comprehensive set of the aforementioned instance types with a uniform algorithm for wirelength, routability, and clock optimization.