Thermal-aware Optical-electrical Routing Codesign for On-Chip Signal Communications
TimeTuesday, July 12th10:30am - 10:52am PDT
Location3007, Level 3
In-Package and On-Chip Communication and Networks-on-Chip
Physical Design and Verification, Lithography and DFM
DescriptionOptical interconnections are promising for signal communication in modern circuit and system designs, providing large bandwidth and high-speed transmission with low power consumption. Previous works do not handle two main issues for on-chip optical-electrical codesign: the thermal impact during optical-electrical routing, and the trade-offs among power consumption, wirelength, and congestion. Consequently, thermal-induced band shift might cause transmission malfunction, and power consumption estimation might be inaccurate. To remedy these disadvantages, we present a thermal-aware optical-electrical routing codesign flow to minimize power consumption, thermal impact, and wirelength. Experimental results show that our flow achieves best-published quality results.