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Presentation

SCAIE-V: An Open-Source SCAlable Interface for ISA Extensions for RISC-V Processors
TimeTuesday, July 12th1:30pm - 1:53pm PDT
Location3004, Level 3
Event Type
Research Manuscript
Keywords
Embedded System Design Methodologies
Time-Critical System Design
Topics
Embedded Systems
RISC-V
DescriptionCustom instructions extending a base ISA are often used to increase performance. However, only few cores provide open interfaces for integrating such ISA Extensions (ISAX). In addition, the degree to
which a core’s capabilities are exposed for extension varies wildly between interfaces. Thus, even when using open-source cores, the lack of standardized ISAX interfaces typically causes high engineering effort when implementing or porting ISAXes. We present SCAIE-V, a highly portable and feature-rich ISAX interface that supports custom control flow, decoupled execution, multi-cycle-instructions, and memory transactions. The cost of the interface itself scales with the complexity of the ISAXes actually used.