Tailor: Removing Redundancy in Memristive Analog Neural Network Accelerators
TimeThursday, July 14th1:52pm - 2:15pm PDT
Location3007, Level 3
Event Type
Research Manuscript
AI/ML Design: Circuits and Architecture
Digital and Analog Circuits
DescriptionAnalog in-situ computation based on memristive circuits has been regarded as a promising way for designing high-performance and low-power neural network accelerators. However, despite the low-cost and highly parallel memristive crossbar itself, peripheral circuit especially analog-digital-converter~(ADC) brings most overhead, which significantly limit the potential of memristive NN accelerators.

To address this problem, we first mathematically analyze the computation flow in a memristive accelerator, and find that there are many useless operations. These operations significantly increase the demand for the peripheral circuits. Then, based on our discovery, we propose a novel architecture, Tailor, which removes these unnecessary operations.