Designing ML-Resilient Locking at Register-Transfer Level
TimeWednesday, July 13th3:30pm - 3:50pm PDT
Location3006, Level 3
Event Type
Research Manuscript
Hardware Security: Attack and Defense
Hardware Security: Primitives, Architecture, Design & Test
DescriptionVarious logic-locking schemes have been proposed to protect hardware from piracy and malicious modifications. Traditionally, locking operates after logic synthesis without semantic design knowledge. However, machine-learning (ML) attacks have been effective in uncovering fundamental flaws within gate-level locking. Recent proposals have focused on register-transfer level (RTL) locking with access to more semantic hardware information. In this work, we investigate the resilience of the ASSURE RTL locking tool against ML-based attacks, thereby uncovering fundamental concepts for ML-resilient locking. The lessons learned are conveyed into two ASSURE-enabled ML-resilient schemes and ML-driven security metrics. The schemes are evaluated against the state-of-the-art SnapShot attack.