VWR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low Power Embedded Devices
TimeWednesday, July 13th4:50pm - 5:10pm PDT
Location3000, Level 3
Design of Cyber-physical Systems, Cloud Computing and IoT
DescriptionEdge-computing requires high-performance energy-efficient embedded systems. Fixed-function accelerators are very efficient for particular functionalities and constraint sets. However, they are inflexible when facing application-wide optimizations or functionality upgrades. Conversely, programmable cores offer higher flexibility, but often with area, performance, and energy penalties. We propose VWR2A, an architecture that integrates high computational density and low power memory structures (i.e., very-wide registers and scratchpad memories). VWR2A narrows the energy gap with similar or better performance on FFT kernels with respect to an FFT accelerator. Moreover, VWR2A offers enough flexibility to accelerate multiple kernels, resulting in significant energy savings at the application level.