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Presentation

A Cost-Efficient Fully Synthesizable Stochastic Time-to-Digital Converter Design Based on Integral Nonlinearity Scrambling
TimeThursday, July 14th2:37pm - 3pm PDT
Location3007, Level 3
Event Type
Research Manuscript
Keywords
AI/ML Design: Circuits and Architecture
Digital and Analog Circuits
Topics
Design
DescriptionStochastic time-to-digital converter (STDC) is gaining increasing interest in submicron CMOS analog/mixed-signal design for its superior immunity to non-linear quantization levels. However, the required large number of delay elements for achieving sufficient accuracy incur excessive implementation costs. This paper presents a fully synthesizable STDC architecture with an associated design flow based on an INL shuffling technique, allowing order-of-magnitude cost reduction. The proposed technique randomizes and averages the TDC INL using a digital-to-time converter. With the proposed design flow, we demonstrate an STDC design in 12nm FinFET process. The post-layout simulations show significant performance improvement compared to the prior arts.