Improving LUT-Based Optimization for ASIC
TimeTuesday, July 12th3:50pm - 4:10pm PDT
Location3007, Level 3
Event Type
Research Manuscript
RTL/Logic Level and High-level Synthesis
DescriptionLUT-based optimization unlocks a clever balance between functionality and structure in logic optimization.
Thus, the LUT-engine framework \cite{lutopto} was introduced to enhance ASIC synthesis.
This work presents novel structure to the flow of LUT-engine, revisiting its requirements for scalability and QoR.
We propose a dedicated LUT mapper and a specialized Boolean factoring technique, providing lightweight LUT-AIG minimization.
We improve 9 of the best area results in the EPFL synthesis competition.
Integrated in a commercial EDA flow for ASICs, over 87 benchmarks, we present: -4.60\% area and -3.41\% switching power at +5\% runtime, comparing to the baseline, over-performing the original LUT-engine.