Write or Not: Programming Scheme Optimization for RRAM-based Neuromorphic Computing
TimeThursday, July 14th10:52am - 11:15am PDT
Location3002, Level 3
Event Type
Research Manuscript
In-memory and Near-memory Computing
DescriptionOne main fault-tolerant method for a neural network accelerator based on resistive random access memory crossbars is write-and-verify (W-V), which will cost huge overhead if all devices are programmed repeatedly. To reduce weight deviations and the overhead, for W-V, we propose a probabilistic termination criterion on a single device and formulate a systematic optimization problem on all devices. Furthermore, we propose a joint algorithm that assists the optimized W-V scheme by incremental retraining, which further reduces the W-V overhead. In experiments, the accuracy drops by 0.94% in ResNet18 on CIFAR10 with less W-V overhead compared to the basic W-V scheme.