TAIM: Ternary Activation In-Memory Computing Hardware with 6T SRAM Array
TimeThursday, July 14th1:53pm - 2:15pm PDT
Location3002, Level 3
Event Type
Research Manuscript
In-memory and Near-memory Computing
DescriptionRecently, various in-memory computing hardware for low-precision neural network have been proposed. While in-memory Binary Neural Network (BNN) accelerators achieved significant performance, BNNs show severe accuracy degradation compared to their full precision counterpart models. In this work, we propose an in-memory computing hardware that can compute a model with ternary activation using 6T SRAM array. Compared to previous designs which support ternary activation, the proposed hardware achieves much higher energy efficiency on various image classification benchmarks.