CP-SRAM: Charge-Pulsation SRAM Marco for Ultra-High Energy-Efficient Computing-in-Memory
TimeTuesday, July 12th11:15am - 11:37am PDT
Location3002, Level 3
In-memory and Near-memory Computing
DescriptionSRAM-based computing-in-memory (SRAM-CIM) provides fast speed and good scalability with advanced process technology. However, the energy efficiency of the state-of-the-art current-domain SRAM-CIM bit-cell structure is limited and the peripheral circuitry (e.g., DAC/ADC) for high-precision is expensive. This paper proposes a charge-pulsation SRAM (CP-SRAM) structure to achieve ultra-high energy efficiency thanks to its charge-domain mechanism. Furthermore, our proposed CP-SRAM CIM supports configurable precision (2/4/6/8-bit). The macro was designed in 180nm (silicon verification) and 40nm (simulation) technology nodes, respectively. The simulation results in 40nm node show that our macro can achieve energy efficiency of 1000-2500Tops/W at 2-bit precision.