Don’t Open Row: Rethinking Row Buffer Policy for Improving Performance of Non-Volatile Memories
TimeWednesday, July 13th4:30pm - 4:50pm PDT
Location3004, Level 3
Embedded Memory, Storage and Networking
DescriptionAmong NVM technologies, phase-change-memory(PCM) has been attracting attention as a candidate to replace the DRAM for the next-generation memory. However, due to the characteristics of PCM, its read and write latencies are much longer than those of DRAM.
This paper proposes Write-Around that tackles this limitation with two novel schemes: Pseudo-Row Activation and Direct Write. Pseudo-Row Activation provides fast row activation for PCM writes by connecting a target row to bitlines, but doesn’t fetch the data into row buffer. With Direct Write scheme, our system allows writing operations to update the data even if target row is logically closed state.