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Presentation

A Scalable SIMD RISC-V based Processor with Customized Vector Extensions for CRYSTALS-Kyber
TimeWednesday, July 13th5:10pm - 5:30pm PDT
Location3005, Level 3
Event Type
Research Manuscript
Keywords
Hardware Security: Primitives, Architecture, Design & Test
Topics
RISC-V
Security
DescriptionThis paper uses RISC-V vector extensions to speed up lattice-based operations in architectures based on HW/SW co-design. We analyze the structure of the number-theoretic transform (NTT), inverse NTT (INTT), and coefficient-wise multiplication (CWM) in CRYSTALS-KYBER, a lattice-based key encapsulation mechanism.
We propose 12 vector extensions for CRYSTALS-KYBER multiplication and three for finite field operations in combination with two optimizations of the HW/SW interface. This results in a speed-up of 141.7, 168.7, and 245.5 times for NTT, INTT, and CWM, respectively, compared with the baseline implementation, and a speed-up of over four times compared with the state-of-the-art HW/SW co-design using RV32I.