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Presentation

PANORAMA: Divide-and-Conquer Approach for Mapping Complex Loop Kernels on CGRA
TimeTuesday, July 12th1:53pm - 2:15pm PDT
Location3007, Level 3
SessionFantastic SoCs and What to Learn!
Event Type
Research Manuscript
Keywords
System-on-Chip Design Methodology
Topics
EDA
Authors
Dhananjaya Wijerathne
National University of Singapore
Zhaoying Li
National University of Singapore
Thilini Bandara
National University of Singapore
Tulika Mitra
National University of Singapore
DescriptionCGRAs are well-suited as hardware accelerators due to power efficiency and reconfigurability. However, their potential is limited by the inability of the compiler to effectively map complex loop kernels onto the architectures. We propose PANORAMA, a fast and scalable compiler based on the divide-and-conquer approach to generate quality mapping for complex dataflow graphs (DFG) representing loop bodies onto larger CGRAs. PANORAMA improves the throughput of the mapped loops by up to 2.6x with a 6.6x faster compilation time compared to the state-of-the-art techniques.