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NovelRewrite: Node-Level Parallel AIG Rewriting
TimeTuesday, July 12th4:10pm - 4:30pm PDT
Location3007, Level 3
Event Type
Research Manuscript
Keywords
RTL/Logic Level and High-level Synthesis
Topics
EDA
DescriptionLogic rewriting is an important part in logic optimization. It rewrites a circuit by replacing local subgraphs with logically equivalent ones, so that the area and the delay of the circuit can be optimized. This paper introduces a node-level parallel AIG rewriting algorithm. Experiments show that this algorithm implemented with one GPU can be up to 50X faster than logic rewriting in the sequential logic synthesis tool ABC. Compared with other logic rewriting acceleration works, ours has the best quality and is the most efficient one in terms of area reduction per second.