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Presentation

Search Space Characterization for Approximate Logic Synthesis
TimeTuesday, July 12th4:30pm - 4:50pm PDT
Location3007, Level 3
Event Type
Research Manuscript
Keywords
RTL/Logic Level and High-level Synthesis
Topics
EDA
DescriptionApproximate logic synthesis aims at trading off a circuit's quality to improve a target metric. Corresponding methods explore a search space by approximating circuit components and verifying the resulting quality of the overall circuit, which is costly.

We propose a methodology that determines reasonable values for the component's local error bounds prior to search space exploration. Utilizing formal verification on a novel approximation miter guarantees the circuit's quality for such local error bounds, independent of employed approximation methods, resulting in reduced runtimes due to omitted verifications. Experiments show speed-ups of up to 3.7x for approximate logic synthesis using our method.