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Presentation

LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
TimeTuesday, July 12th11:37am - 12pm PDT
Location3007, Level 3
Event Type
Research Manuscript
Keywords
In-Package and On-Chip Communication and Networks-on-Chip
Physical Design and Verification, Lithography and DFM
Topics
EDA
DescriptionPrecise congestion spot prediction from a placement solution plays a crucial role in the VLSI placement optimization. This work proposes LH-graph, a novel graph formulation for VLSI, which enables the congestion information to be propagated geometrically and topologically and can automatically generate conventional crafted features. Base on our formulation, we developed a heterogeneous graph neural network architecture LHNN, jointing the routing demand regression to support the congestion spot classification. LHNN constantly achieves more than {\bf 35\%} improvements compared with U-nets and GAN on the F1 score. We expect our work shall identify essential procedures using machine learning for congestion prediction.