GEML: GNN-Based Efficient Mapping Method for Large Loop Applications on CGRA
TimeTuesday, July 12th4:50pm - 5:10pm PDT
Location3005, Level 3
Event Type
Research Manuscript
SoC, Heterogeneous, and Reconfigurable Architectures
DescriptionCoarse-grained reconfigurable architecture (CGRA) is an emerging hardware architecture, with reconfigurable Processing Elements (PEs) for executing operations efficiently and flexibly. One major challenge for current CGRA compilers is the scalability issue, where valid loop mapping results cannot be obtained in acceptable time. This paper proposes an enhanced loop mapping method based on Graph Neural Network (GNN), which effectively adresses the scalability issue and generates valid loop mapping results for typical applications. Experimental results show that the proposed method enhances the compilation time by 10x over state-of-the-art techniques, with even better loop mapping solutions.