An Efficient Yield Optimization Method for Analog Circuits via Gaussian Process Classification and Varying-Sigma Sampling
TimeWednesday, July 13th2:30pm - 3pm PDT
Location3004, Level 3
Analog Design, Simulation, Verification and Test
DescriptionTo quickly determine the better design, yield estimations are executed at varying sigma of process variations. Instead of regression methods requiring accurate yield values, a Gaussian process classification method is applied to model these preference information of designs with binary comparison results, and the preferential Bayesian optimization framework is implemented to guide the search. we also use a multi-fidelity surrogate model to learn the yield correlations at different sigmas, and utilize the results from nominal performance optimization to warm-start the yield optimization. Compared with the state-of-the-art methods, the proposed method achieves up to 10x speed-up without loss of accuracy.