CREAM: Computing in ReRAM-assisted Energy and Area-efficient SRAM for Neural Network Acceleration
TimeTuesday, July 12th11:37am - 12pm PDT
Location3002, Level 3
In-memory and Near-memory Computing
DescriptionComputing-in-memory has been widely explored to accelerate DNN. However, most existing CIM cannot store all NN weights due to limited SRAM capacity, inducing large amount off-chip DRAM accesses. In this paper, a new computing in ReRAM-assisted energy and area-efficient SRAM (CREAM) is proposed. The weights of DNN are stored in the high-dense on-chip ReRAM devices and restored to the nvSRAM-CIM with array-level parallelism. A data-aware weight-mapping method is also proposed to enhance the CIM performance with maximized hardware utilization. The proposed CREAM enhances the storage density and energy-efficiency by up to 7.94x and 2.14x, respectively, compared to current SRAM-CIM circuits.