SAPredictor: A Simple and Accurate Self-adaptive Predictor for Hierarchical Hybrid Memory System
TimeWednesday, July 13th5:10pm - 5:30pm PDT
Location3004, Level 3
Embedded Memory, Storage and Networking
DescriptionIn a hybrid memory system that uses DRAM as the NVM cache, DRAM and NVM can be accessed in serial mode or parallel mode. However, using either mode alone incurs long access latency and degrades memory performance. In this paper, we propose to combine these two modes and design a very simple predictor to predict access patterns and choose the right access modes, thus avoiding long access latencies either when DRAM hits or misses. Our experiments show that our predictor reaches above 95% accuracy and reduces the access latency by approximately 30%, while costing only dozens of K bytes.