High-performance Placement for Large-scale Heterogeneous FPGAs with Clock Constraints
TimeWednesday, July 13th2:15pm - 2:37pm PDT
Location3007, Level 3
Physical Design and Verification, Lithography and DFM
DescriptionThis paper presents a high-performance placement algorithm for large-scale heterogeneous FPGAs with clock constraints. We first propose a connectivity-aware and type-balanced clustering method to improve the scalability. Then, we develop a novel hybrid penalty and augmented Lagrangian method to formulate placement as an unconstrained optimization subproblem and adopt the Adam method to solve each subproblem. Furthermore, a multi-stage packing technique is proposed to cluster FFs and LUTs into CLBs, and history-based legalization is developed to legalize CLBs. Experimental results show that our algorithm achieves the smallest routed wirelength among all published works in a reasonable runtime.