A Defect Tolerance Framework for Improving Yield
TimeWednesday, July 13th3:54pm - 4:18pm PDT
Location3007, Level 3
Manufacturing Test and Reliability
DescriptionWe propose a framework for improving yield of a fabricated design in the presence of manufacturing defects. Specifically, through standard library cell timing characterization in the presence of defects and subsequent defect-aware synthesis, we generate netlists with improved ability to withstand delays induced by process imperfections. We also introduce defect tolerance metrics to quantify robustness to process imperfections, which we use to guide defect-aware synthesis. Effectiveness is evaluated on a set of benchmarks implemented in a 12nm node, revealing a 70-80% reduction of yield loss due to timing errors arising from manufacturing defects, with minimum impact on area and power.