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Presentation

A scalable symbolic simulation tool for low power embedded systems
TimeTuesday, July 12th1:53pm - 2:15pm PDT
Location3004, Level 3
Event Type
Research Manuscript
Keywords
Embedded System Design Methodologies
Time-Critical System Design
Topics
Embedded Systems
RISC-V
DescriptionUsing Symbolic Simulation, Bespoke optimization techniques have proven their feat in generating processor designs tailored for a particular application. However, current state-of-the-art symbolic simulation tools are restricted to one design as the prior work uses a custom tool supporting only that design. To scale the technique to any processor's design, we propose a custom symbolic simulator that uses iVerilog to perform symbolic behavioral simulation. With Iverilog, an open-source verilog synthesis and simulation tool, we implement and show the benefits of bespoke optimizations on four embedded system processors - a MIPS-based, RISV-based, MSP430, and ARM cortex-M0.