High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
TimeTuesday, July 12th10:30am - 10:53am PDT
Location3004, Level 3
Event Type
Research Manuscript
RTL/Logic Level and High-level Synthesis
DescriptionThis work aims to significantly expedite the circuit evaluation at its earliest stage, High-level Synthesis (HLS). We propose rapid and accurate performance modeling using graph neural networks (GNNs) by representing C/C++ programs as graphs. Our contribution is three-fold: (1) we build a comprehensive benchmark suite containing 40k synthesizable programs including three sets of real-world HLS benchmarks; (2) we analyze 14 state-of-the-art GNN models aiming at providing domain-specific knowledge for designing GNNs; (3) we further propose a novel hierarchical GNN to improve the prediction accuracy. Our proposed model largely outperforms commercial HLS tools.