Canceled: Delivering “Smarter” Faster: The Future of EDA & AI
TimeMonday, July 11th1pm - 1:45pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall
DescriptionEDA and IC design are areas rife with opportunity for AI due to the massive datasets involved. Today’s cutting-edge CPU and ASICs are measured in the tens of billions of transistors, straining EDA capabilities. This is leading to dramatically higher computational demand for IC design flow. As designs shrink from 7nm to 2nm, the number of CPU cores needed for these tasks is soaring into the thousands to maintain the same turnaround time.
In the past several years, EDA has made significant progress in applying machine learning and AI to increase the performance, accuracy and capacity of its offerings. This has appreciably lowered computational resources while improving throughput. But challenges still remain. Though many areas of EDA can drive a significant decrease in computational load through AI/ML techniques, other’s require an exactness of outcome that goes beyond current capabilities. Joe Sawicki, executive vice president, IC Siemens EDA, will survey the substantial improvement reaped thus far from incorporating AI/ML into EDA toolsets. And then he will explore where EDA should focus its resources and efforts to realize the full promise of AI and EDA.