Accelerator Design with Decoupled Hardware Customizations: Benefits and Challenges
TimeWednesday, July 13th4pm - 4:30pm PDT
Location3003, Level 3
Event Type
Special Session (Research)
DescriptionCurrent High-Level Synthesis (HLS) programming models entangle algorithm specifications with hardware customization techniques, which lowers both the productivity and portability of the accelerator design. To solve this problem, recent work such as HeteroCL proposes to decouple algorithm definition from essential hardware customization techniques in compute, data type, and memory. While the decoupling of the algorithm and customizations provides benefits to the compilation/synthesis process, they also create new hurdles for the programmers to debug and validate the correctness of the optimized design. In this work, using realistic ML applications, we first explain the advantages of the decoupled programming model. Using the same case studies, we further show how seemingly benign usage of the customization primitives can lead to new challenges to verification. We then outline the research opportunities and discuss some of our recent efforts as the first step to enable a robust and viable verification solution in the future.