Presentation
ScaleHLS: a Scalable High-Level Synthesis Framework with Multi-level Transformations and Optimizations
TimeWednesday, July 13th4:30pm - 5pm PDT
Location3003, Level 3
Event Type
Special Session (Research)
EDA
DescriptionThis paper presents an enhanced version of a scalable HLS (High-Level Synthesis) framework named ScaleHLS, which can compile HLS C/C++ programs and PyTorch models to highly-efficient and synthesizable C++ designs. The original version of ScaleHLS achieved significant speedup on both C/C++ kernels and PyTorch models. In this paper, we first highlight the key features of ScaleHLS on tackling the challenges present in the representation, optimization, and exploration of large-scale HLS designs. To further improve the scalability of ScaleHLS, we then propose an enhanced HLS transform and analysis library supported in both C++ and Python, and a new design space exploration algorithm to handle HLS designs with hierarchical structures more effectively. Comparing to the original ScaleHLS, our enhanced version improves the speedup by up to 60.9x on FPGAs. ScaleHLS is fully open-sourced at https://github.com/hanchenye/scalehls.