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Presentation

par-gem5: Parallelizing gem5’s Atomic Mode
TimeTuesday, July 12th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionWe propose par-gem5 - the first universally parallelized version of the Full System Simulator (FSS) gem5.
It exploits the host system's multi-threading capabilities using a modified conservative parallel discrete event simulation.
Compared to other parallel approaches, par-gem5 uses relaxed causality constraints. This allows temporal errors, but we show that the system's functional correctness is retained.
Furthermore, we extend par-gem5 by a temporal error estimation that assesses the accuracy of a simulation without a sequential reference simulation.
Our experiments reached speedups of 24.7x when simulating a 128-core MPSoC on a 128-core host system.
Simulation statistics are accurate to a single-digit percentage.