Bridger: Fast Token Delivery in Elastic Circuits
TimeTuesday, July 12th6pm - 7pm PDT
LocationLevel 2 Lobby
DescriptionHigh-level synthesis (HLS) is the process of automatically generating an RTL design out of a high-level language. Previous research has shown that dynamically scheduled HLS through dataflow circuit generation is successful at exploiting parallelism in some use-cases. Nevertheless, the direct generation of dataflow circuits from high-level input, typically, produces circuits with notable resource demands and subpar frequency. In this work, we present a methodology for generating area- and timing-efficient dataflow circuits from imperative code. We show that our strategy results in significant area and frequency improvements compared to recent HLS-based dataflow circuit generation strategies.