Design Space Exploration of Mixed-Precision Hardware Accelerators for CNNs
TimeTuesday, July 12th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionConvolutional Neural Networks (CNNs) reach high accuracies in various fields while requiring significant amounts of computations and incurring costly data movements. Besides others, reduction in word-length of weights and/or activations allows balancing cost vs. accuracy. Thereby, mixed-precision layer-wise quantization provides more efficient results while inflating the design space. This work presents a quantitative methodology for efficient Design Space Exploration supporting combined optimization of processing elements and dataflow. The resulting hardware architectures efficiently support layer-wise and channel-wise quantized CNNs, i.e., realizes true mixed-precision hardware accelerators. Mapping ResNet-18 and ResNet-152 results in 271.7 frames/s and 1.13 TOps/s, respectively.