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Presentation

Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP
TimeTuesday, July 12th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionLogic locking has become a promising approach to provide hardware security in the face of a possibly-insecure fabrication supply-chain. While many techniques have focused on locking combinational logic, an alternative latch-locking approach, in which the sequential elements are locked, has gained significant attention. This paper presents a two-phase attack on latch-locked circuits that uses a novel combination of deep learning, Boolean analysis, and ILP. The attack requires access to the reverse-engineered netlist but, unlike SAT attacks, is oracle-less. The attack was evaluated using the ISCAS'89 and ITC'99 benchmark circuits and successfully identifies a key that is, on average, 98.0% accurate.