A Linear Column-Major Capacitance Multiplier based Analog In-Memory Computing Architecture
TimeTuesday, July 12th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionAnalog Based In-Memory Computing using 6T SRAM promises high throughput and energy efficiency. However, the linearity and dynamic range of the output are a significant concern. To maintain linearity, often, high capacitance and/or short wordline pulse are required. In this work, we proposed column-major analog IMC architecture with a capacitive multiplier with improved linearity and dynamic range. The proposed capacitive multiplier architecture occupies extremely less area and generates high capacitance. We have performed a post-layout simulation for 128x128 memory array architecture. We have achieved an energy efficiency of 25.6 TOPS/W for 4bit multiplication.