Heterogeneous Chiplet-based Architecture for In-Memory Acceleration of DNNs: A Big-Little Approach
TimeTuesday, July 12th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionIn-memory computing (IMC) with a monolithic chip faces dramatic challenges in yield and fabrication cost as the complexity of DNNs keeps increasing. Chiplet-based IMC offers a practical solution using advanced 2.5D/3D packaging. To reduce the overhead in network-on-package (NoP), we recognize algorithmic variations across DNN layers and propose a heterogeneous big-little approach. The new solution tailors the computation and communication resource to the target DNN, with an interposer for the little cores and a bridge structure for the big cores. Evaluations with a wide range of DNNs demonstrate significant improvement in performance with superior area- and energy efficiency.