A method for hierarchical, transistor-level circuit simulation
TimeWednesday, July 13th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionThis paper proposes and outlines a novel method to hierarchically simulate circuits at the transistor level with true SPICE accuracy. Unlike traditional SPICE simulators, which flattens all the subcircuit instances, the proposed method maintains the hierarchical nature of circuit design and enables almost 100% of matrix-solving parallelization by leveraging both bottom-up and top-down processes along circuit hierarchy. This new method generates identical results to those from traditional SPICE, provides the ability to set multi-precision for different subcircuit instances within the same simulation session, and is easily adaptable to SIMD computation.