MuZero-guided Simulated Annealing for Nanometer Circuit Placement
TimeTuesday, July 12th6pm - 7pm PDT
LocationLevel 2 Lobby
DescriptionAnalog circuit placement has been a longstanding problem ascribing to ever-increasing design constraints and intricate physical effects. Concentration on developing optimal constraint-specific algorithms is not cost-effective in industrial settings. By contrast, a set of fundamental geometric rules is sufficient to suggest preliminary drafts. In this paper, we propose a placement tool for fast drafting. A learning-based method is incorporated to guide simulated annealing to avoid local optima. Empirical results on TSMC 3nm circuits demonstrate that the development time, with our method in cooperation with designers, can be reduced from days to minutes.