Equivalence Checking for Agile Hardware Design
TimeWednesday, July 13th6pm - 7pm PDT
LocationLevel 2 Lobby
DescriptionThe industries are showing a growing interest in heterogeneous hardware architectures. However, developing high-performance code for those architectures requires specialized knowledge of the target hardware. HeteroCL decouples design specifications from hardware customizations to solve this issue. This paper presents an equivalence checking framework for certifying two HeteroCL designs and implements optimizations to eliminate complexities caused by HeteroCL. In our experiments, our framework successfully detected inconsistencies in multiple deep-learning accelerator designs generated by HeteroCL from Intel that manually written unit tests fails to identify.