LDAVPM: A Latch Design with Algorithm-based Verification Protected against Multiple-Node-Upsets in Harsh Radiation Environments
TimeWednesday, July 13th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionIn deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to multiple-node upsets (MNUs) in harsh radiation environment. Muller C-elements are widely used in recent years for latch hardening against MNUs. Existing latch verifications for error-recovery highly rely on EDA tools. In this paper, a latch design with algorithm-based verification protected against MNUs is proposed. Due to the formed redundant feedback-loops, the latch can completely recover from any MNU. Algorithm-based verification results demonstrate the MNU-recovery of the proposed latch. Simulation results demonstrate the low-area overhead of the proposed latch compared with the only one existing same-type design.