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Presentation

Constructing Large Buffers with HeterogeneousSTT-RAM Cells for DNN Accelerators
TimeWednesday, July 13th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionDeep Neural Networks (DNN) Inference on mobile and edge devices is challenging due to its high computation and storage demands. This paper presents a DNN accelerator architecture incorporating large buffers implemented with spin-transfer torque magnetic random-access memory (STT-RAM). To stash entire filters of a DNN model in a buffer, STT-MRAM cells are optimized to reduce their feature size. For the buffer holding activations, STT-MRAM cells are optimized to reduce the write latency. The experimental results demonstrate the DNN accelerators with the optimized buffers achieve the speedup of 143% and energy saving of 60.5% on average.