ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
TimeWednesday, July 13th6pm - 7pm PDT
LocationLevel 2 Lobby
Event Type
Networking Reception
Work-in-Progress Poster
DescriptionA two-phase chip performance prediction flow is presented. In phase I, we predict the initial value of minimum operating voltage (Vmin). In phase II, we predict the bin for each chip to apply different guard bands. Experiments on 851 advanced 7nm mobile chips show that predicted Vmin is larger than actual Vmin for all chips to avoid customer return. Also, power consumption is reduced by 2.69%. Yield loss is mitigated by up to 5.05% when our Vmin requirement is 1.20 scaled Vmin. Our flow can save the long time of measuring Vmin for every chip with little runtime overhead.